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SPC500A1
512KB SOUND CONTROLLER
GENERAL DESCRIPTION
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The SPC500A1 is a CPU based two-channel speech/melody synthesizer including CMOS 8-bit microprocessor with 69 instructions, 512K-byte ROM for speech and melody data (Speech is compressed by a 4-bit ADPCM with approx. 120 sec speech duration @ 7KHz sampling rate) and 128-byte working SRAM. It includes two Timer/Counters, 23 Software Selectable I/Os, two 8-bit current outputs D/A (or one PWM audio output) and serial interface I/O port. It provides Multi-Duty-Cycle output for remote control purposes. For audio
processing, melody and speech can be mixed into one output.
It operates over a wide voltage range of 2.4V -
5.5V and includes Low Voltage Reset function. The Low Voltage Reset automatically resets when the working voltage is less than 2.2V. Volume control is provided. In addition, the SPC500A1 has a Clock Stop mode for
power savings. The power savings mode saves the RAM contents, but freezes the oscillator, causing all other chip functions to be inoperative. The Max. CPU clock frequency is 8.0MHz. It has an Instruction Cycle Rate of 2 clock cycles (min.) - 6 clock cycles (max.). The SPC500A1 includes, not only the latest technology, but also the full commitment and technical support of Sunplus.
FEATURES 8-bit microprocessor Provides 512K-byte ROM for program and audio data 128-byte working SRAM Software-based audio processing Wide operating voltage: 2.4V - 3.4V@ 5.0MHz 3.6V - 5.5V@ 8.0MHz Supports Crystal Resonator or Rosc (with Mask option) Max. CPU clock: 5.0MHz@3V, 8.0MHz@5V Two 12-bit timer/counters Standby mode (Clock Stop mode) for power savings. Max. 2 A @ 5V 500ns instruction cycle time @ 4.0MHz CPU clock 6 INT sources Key wake -up function Provides 23 general I/Os Serial interface I/O Approx. 120 sec speech @ 7KHz sampling rate with ADPCM One PWM audio output (single speaker) Two DA output Multi-duty cycle mode Sunplus Technology Co., Ltd. 1 APPLICATION FIELD Intelligent education toys Ex. Pattern to voice (animal, car, color, etc.) Spelling (English or Chinese) Math High end toy controller Talking instrument controller General speech synthesizer Industrial controller Rev.: 1.0 1999.11.04
IOA3-0 (I/O) 23 PINS GENERAL I/O XI Rosc XO CLK OSC Low Voltage Reset 8-bit RISC controller
Low Voltage Reset Volume control function
BLOCK DIAGRAM
512K-byte ROM Two Timers TimeBase INT control
128-byte SRAM Two 8-bit D/A (current) or PWM output
AUD1
AUD2
Serial interface I/O PORT
IOB3-0 (I/O)
IOC6-0 (I/O)
IOD7-0 (I/O)
SPC500A1
FUNCTION DESCRIPTIONS
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CPU
The 8-bit microprocessor of SPC500A1 is a high performance processor equipped with Accumulator, Program Counter, X Register, Stack pointer and Processor Status Register (this is the same as the 6502 instruction structure). SPC500A1 is able to perform with 8.0MHz (max.) depending on the application specifications.
OSCILLATOR The SPC500A1 supports AT-cut parallel resonant oscillated Crystal / Resonator or RC Oscillator or external clock sources by mask option (select one from those three types). The design of application circuit should follow the vendors' specifications or recommendations. The diagrams listed below are typical X'TAL/ROSC circuits for most applications:
SPC500A1
XI/R XO
VDD Rosc 20 pf 20 pf
SPC500A1
XI/R XO
(a) Crystal or Ceramic Resonator Connections
(b) RC Oscillator Connections
MASK OPTION The SPC500A1 has the following mask option: Supports Crystal Resonator or Rosc (with mask option).
ROM AREA The SPC500A1 provides a 512K-byte ROM that can be defined as the program area, audio data area, or both. To access ROM, users should program the BANK SELECT Register, choose bank, and access address to fetch data.
RAM AREA The SPC500A1 total RAM consists of 128 bytes (including Stack) at locations from $80 through $FF.
VOLUME CONTROL FUNCTION The SPC500A1 contains a volume control function that provides an 8-step volume controller to control current D/A output. A volume control function selector (Enable/Disable) register and controller register is provided.
Sunplus Technology Co., Ltd.
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SPC500A1
MAP OF MEMORY AND I/Os
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*I/O PORT:
*MEMORY MAP (From ROM view) $0004 $0005 $00080 USER RAM and STACK $00000 HW register, I/Os
- PORT IOA IOB
- I/O CONFIG $0000 $0001
$00100 UNUSED $00200
*NMI SOURCE: - INTA (from TIMER A) $00600
SUNPLUS TEST PROGRAM
*INT SOURCE: - INTA (from TIMER A) - INTB (from TIMER B) - CPU CLK / 1024 - CPU CLK / 8192 - CPU CLK / 65536 - EXT INT $7FFFF $18000 $08000
USER'S PROGRAM & DATA AREA ROM BANK #0 ROM BANK #1 $10000 ROM BANK #2
ROM BANK #15($0F)
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SPC500A1
I/O PORT CONFIGURATIONS*
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Input/Output IOA port : IOA3 - IOA0 logic_1 control output data buffer or OD-NMOS V DD
Input/Output IOB port : IOB3 -IOB0 input data
100K output data logic_2 control OD : Open Drain 70K OD-NMOS or buffer
input data OD : Open Drain
Input/Output IOC port : IOC3 - IOC0 logic_3 control output data buffer or OD-NMOS V DD 100K
Input/Output IOC port : IOC6 - IOC4 logic_4 control output data buffer or OD-NMOS V DD 100K
input data OD : Open Drain
input data OD : Open Drain
Input/Output IOD port : IOD3 - IOD0 input data OD-PMOS or buffer
Input/Output IOD port : IOD7 - IOD4 input data OD-PMOS or buffer
output data logic_5 control OD : Open Drain
output data 70K logic_6 control OD : Open Drain
70K
*Values shown are for VDD = 5.0V test conditions only.
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SPC500A1
POWER SAVINGS MODE
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The SPC500A1 provides a power savings mode (Standby mode) for those applications that require very low stand-by current. To enter standby mode, the Wake-Up Register should be enabled and then stop the CPU In such a mode,
clock by writing the STOP CLOCK Register. The CPU will then go to the stand-by mode. RAM and I/Os will remain in their previous states until being awakened. 65536 x T1) and then continue processing the program. FIG.1).
Port IOD7-0 is the only wake-up
source in the SPC500A1. After the SPC500A1 is awakened, the internal CPU will go to the RESET State (Tw Wakeup Reset will not affect RAM or I/Os (See
Sleep T1 CPU CLK Reset
Wake-up
Tw
FIG. 1 T1 = 1 / ( FCPU ), Tw 65536 x T1
LOW VOLTAGE RESET The SPC500A1 provides a Low Voltage Reset (LVR) function. Below the minimum power-supply voltage of 2.2V, the CPU system will become unstable and malfunction. Low Voltage Reset will reset all functions into
the initial operational (stable) state if the VDD power-supply voltage drops below 2.2V (See FIG.2).
T1
CPU CLK VDD
2.2V
T2
RESET T2
TW
A 2 * T1
(The LVR function is the same as Power ON Reset or External Reset.) FIG. 2
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SPC500A1
TIMER/COUNTER
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The SPC500A1 contains two 12-bit timer/counters, TMA and TMB respectively. TMA can be specified as a timer or a counter, but TMB can only be used as a timer. In the timer mode, TMA and TMB are re-loaded upcounters. When timer overflows from $0FFF to $0000, the carry signal will make the timer automatically reload to the user's pre-set value and be up-counted again. At the same time, the carry signal will generate the INT signal if the corresponding bit is enabled in the INT ENABLE Register. If TMA is specified as a counter, users can reset by loading #0 into the counter. After the counter has been activated, the value of the counter can also be read from the counters at the same time.
Clock source of Timer/Counter can be selected as follows: Timer/Counter TMA 12-BIT TIMER 12-BIT COUNTER TMB 12-BIT TIMER Clock Source CPU CLOCK (T) or T/4 T/64, T/8192, T/65536 or EXT CLK T or T/4 TMA only, select timer or counter Select T or T/4
MODE SELECT REGISTER TIMER CLOCK SELECTOR
SPEECH AND MELODY Since the SPC500A1 provides a large ROM and wide range of CPU operation speeds, it is most suitable for speech and melody synthesis. frequency. For speech synthesis, the SPC500A1 can provide NMI for accurate sampling
Users can record or synthesize the sound and digitize it into the ROM. The sound data can be
played back in the sequence of the control functions as designed by the user's program. Several algorithms are recommended for high fidelity and compression of sound including PCM, LOG PCM, and ADPCM. For melody synthesis, the SPC500A1 provides the dual tone mode. After selecting the dual tone mode, users only
need to fill either TMA or TMB, or both TMA and TMB to generate expected frequency for each channel. The hardware will toggle the tone wave automatically without entering into an interrupt service routine. Users are able to simulate musical instruments or sound effects by simply controlling the envelope of tone output.
SERIAL INTERFACE I/O The SPC500A1 provides serial interface I/O mode for those applications requiring large ROM/RAM. Serial
Interface I/O Port can be used to read/write data from/to extra memory. The interface I/O Register is the control register for programming interface I/O.
MULTI-DUTY CYCLE MODE The SPC500A1 provides three output waveforms, 1/2, 1/3, and 1/4 duty cycles. The Control Register should be used to select 1/2, 1/3 or 1/4 duty cycle and the IOA2 should be programmed as the multi-duty cycle output port. Users can use the combinations of these duty cycles for remote-control purposes. Sunplus Technology Co., Ltd. 6 Rev.: 1.0 1999.11.04
SPC500A1
1/2, 1/3, 1/4 duty cycle outputs
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Clock
1/2 duty cycle
1/3 duty cycle 1/4 duty cycle
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SPC500A1
PIN DESCRIPTIONS*
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Mnemonic VDD VSS XI
PIN No. 11,15 1,10 13
Type I I I
Description Positive supply for logic and I/O pins Ground reference for logic and I/O pins Oscillator crystal input or RESISTOR (Resistor should be connected to VDD)
XO TEST RESET AUD1 AUD2
12 17 2 14 16
O I I O
Oscillator crystal output TEST MODE This pin is an active low reset to the chip AUDIO OUTPUT
Port A is an 4-bit bi-directional programmable Input / Output port with PullIOA0 IOA1 IOA2 IOA3 30 31 32 33 I/O I/O I/O I/O high or Open-drain option. Pull-high states. As inputs, Port A can be in either the Pure or
As outputs, Port A can be either Buffer or Open-drain
NMOS types (Sink current). IOA0: Serial programming clock output IOA2: Multi-duty cycle output **See note 1 and 2 below. Port B is an 4-bit bi-directional programmable Input / Output port with Pull-
IOB0 IOB1 IOB2 IOB3
26 27 28 29
I/O I/O I/O I/O
low or Open-drain option.
As inputs, Port B can be in either the Pure or
Pull-low states. As outputs, Port B can be either Buffer or Open-drain NMOS types (Sink current). **See note 1 and 2 below. Port C is an 7-bit bi-directional Input / Output port with Pull-high or Open-
IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6
3 4 5 6 7 8 9
I/O I/O I/O I/O I/O I/O I/O
drain option.
As inputs, Port C can be in either the Pure or Pull-high
states. As outputs Port C can be a Buffer type or Open-drain NMOS type (sink current). IOC0: Serial programming Data IOC1: Can also be selected as an external interrupt PIN IOC2: EXT COUNT IN **See note 1 and 2 below.
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SPC500A1
Mnemonic
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PIN No.
Type
Description Port D is an 8-bit bi-directional programmable Input / Output port with Pull-
IOD0 IOD1 IOD2 IOD3 IOD4 IOD5 IOD6 IOD7
18 19 20 21 22 23 24 25
I/O I/O I/O I/O I/O I/O I/O I/O
low or Open-drain option.
As inputs, Port D can be either Pure or Pull-low
states. As outputs, Port D can be either Buffer or Open-drain PMOS type (send current). (Port D can be software programmed for wake up I/O PIN) (Programmable I/O, Key change, Wake up I/O)
**See note 1 and 2 below.
* Refer to SPC Programming Guide for complete information. **Note: 1.) Two input states can be specified; Pure Input, Pull-High or Pull Low. 2.) Three output states can be specified, Buffer output, Open Drain PMOS output , Open Drain NMOS output .
ABSOLUTE MAXIMUM RATINGS Characteristics DC Supply Voltage Input Voltage Range Operating Temperature Storage Temperature Symbol V+ VIN TA TSTO Ratings < 7V -0.5V to V+ + 0.5V 0 -50 to +60 to +150
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions see AC/DC Electrical Characteristics.
AC CHARACTERISTICS ( TA = 25 Characteristics Symbol
) Limit Unit Min. Typ. 3.58 4.0 Max. 5.0 8.0 MHz MHz VDD = 3V VDD = 5V Test Condition
CPU Clock
FCPU
-
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SPC500A1
DC CHARACTERISTICS ( TA = 25
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, VDD = 3V ) Limit Unit Min. Typ. 1.5 -1.5 Max. 3.4 2.0 2.0 0.8 V mA A mA V V mA For 2-battery FCPU = 3.0MHz @ 3V, no load VDD = 3V VDD = 3V, one-channel VDD = 3V VDD = 3V VDD = 3V VOH = 2V VDD = 3V VOL = 0.8V Pull Low VDD = 3V 2.4 2.0 -1.0 Test Condition
Characteristics
Symbol VDD IOP ISTBY IAUD VIH VIL IOH
Operating Voltage Operating Current Standby Current Audio output current Input High Level Input Low Level Output High I IOA,IOB,IOC,IOD Output Sink I IOA,IOB,IOC,IOD Input Resistor IOB,IOD
IOL
2.0
-
-
mA
RIN
-
100
-
Kohm
DC CHARACTERISTICS ( TA = 25 Characteristics Operating Voltage Operating Current Standby Current Audio output current Input High Level Input Low Level Output High I IOA,IOB,IOC,IOD Output Sink I IOA,IOB,IOC,IOD Input Resistor IOB,IOD Symbol
, VDD = 5V ) Limit Unit Min. Typ. 4.0 -3.0 Max. 5.5 5.0 2.0 0.8 V mA A mA V V mA For 3-battery FCPU = 4.0MHz @ 5V, no load VDD = 5V VDD = 5V, one-channel VDD = 5V VDD = 5V VDD = 5V VOH = 4.2V VDD = 5V VOL = 0.8V Pull Low VDD = 5V 3.6 3.0 -1.0 Test Condition
VDD IOP ISTBY IAUD VIH VIL IOH
IOL
4.0
-
-
mA
RIN
-
70
-
Kohm
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Rev.: 1.0
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SPC500A1
The relationship between the Rosc and the FCPU
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VDD = 3.0V , Ta = 25
VDD = 5.0V , Ta = 25
6.0

FCPU ( MHz )
5.0 4.0 3.0 2.0 1.0 0.0
A A
A

0
200
400
600
800
Rosc ( Kohms )
Frequency vs. Temperature
Frequency normalized to 25 1.04 FCPU/FCPU(25 )
Frequency vs. VDD
4 FCPU ( MHz )
Rosc=100Kohms
1.02 1.00
3 2 1
VDD=5.0V
Rosc = 100 Kohms
VDD=3.0V
0.98 0.96 0 10 20 30 40 50 Temperature ( ) 60 70
Rosc = 360 Kohms
0 2.0
3.0
4.0
5.0
VDD ( Volts )
Operating current vs. Frequency vs. VDD
5.0 4.0 IOP ( m A ) 3.0 2.0 1.0 0.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 FCPU ( MHz )
VDD = 3V VDD = 5V
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SPC500A1
VDD
VDD
VDD
C3 20p
C4 Speaker 20p Q1 8050D IOA3 - 0
IOA (I/O)
R1 Resistor
Speaker
XI
XO
IOA3 - 0
IOA (I/O)
C1 + 0.47 F
XI
XO
C1 + 0.47 F
Q1 8050D
IOC6 - 0
IOC (I/O)
AUD1
IOC6 - 0
IOC (I/O) VDD
AUD1
IOB3 - 0
IOB(I/O)
VDD AUD2
IOB3 - 0
IOB(I/O)
VDD AUD2
IOD7 - 0
IOD (I/O) VSS
C6 0.1 Speaker Q2 8050D
IOD7 - 0
IOD (I/O) VSS
C4 0.1 Speaker Q2 8050D C2 + 0.47 F
R1 VDD
APPLICATION CIRCUIT NOTES
RESET
R2 VDD 50K C3 C2 + 0.47 F
RESET
50K
Application Circuit Note (1)
C5 RESET 0.1
0.1
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SPC500A1 Application circuit (D/A Output)
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RESET
12
SPC500A1
SPC500A1
VDD
Rev.: 1.0
X'TAL/CERAMIC OSC
1999.11.04
SPC500A1
X'TAL/CERAMIC OSC C3 20p
VDD
VDD SCL CSB SDA VSS
VDD
VDD
VDD
C4 Speaker 20p
VDD
R1 Resistor Q1 8050D
SPRS 256A
Speaker
XI
IOA0 IOA1 IOA2 IOA3 IOC0
XO
SPRS 256A
C1 + 0.47 F
VDD SCL CSB SDA VSS
XI IOA0 IOA1 IOA2 IOA3 IOC0
XO
C1 + 0.47 F
Q1 8050D
AUD1
AUD1
IOC6-1 IOB3-0
SPC500A1
IOC(I/O)
IOC6-1
VDD
SPC500A1
IOC(I/O)
VDD
VDD AUD2
VDD
IOB(I/O)
IOB3-0
IOB(I/O)
AUD2
IOD7-0
IOD (I/O)
VSS
C6 0.1 Speaker Q2 8050D C2 + 0.47 F
IOD7-0
IOD (I/O) VSS RESET
C4 0.1 Speaker
R1 VDD 50K
Application Circuit Note (2)
RESET
R2 VDD 50K C3
RESET 0.1
RESET 0.1
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SPC500A1 Application circuit with Serial Interface I/O Application
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C5
Q2 8050D C2 + 0.47 F
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SPC500A1
X'TAL/CERAMIC OSC C3 20p C4 20p
VDD
R1 Resistor
XI
XO
XI
XO
IOA3-0
IOA (I/O)
IOA3-0
IOA (I/O) AUD1 IOC (I/O)
IOC6-0
IOC6-0
IOC (I/O) Speaker ~16
AUD1
SPC500A1
IOB3-0
IOB(I/O) VDD AUD2
SPC500A1
IOB3-0
IOB(I/O) VDD AUD2
Speaker ~16
IOD7-0
IOD (I/O) VSS RESET
IOD7-0 0.1
IOD (I/O) VSS RESET
0.1
R1 VDD 50K
Application Circuit Note (3)
R2 VDD 50K
RESET 0.1 0.1
RESET
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SPC500A1 Application circuit (PWM Output)
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C5
C3
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SPC500A1
X'TAL/CERAMIC OSC C3 20p
VDD XI
VDD
VDD
C4 20p
VDD XO XI XO
VDD SCL CSB SDA VSS
R1 Resistor
SPRS 256A
SCL CSB SDA VSS
IOA0 IOA1 IOA2 IOA3 IOC0
SPRS 256A
AUD1
IOA0 IOA1 IOA2 IOA3 IOC0
AUD1
IOC6-1
SPC500A1
IOC(I/O) VDD IOB(I/O) AUD2
Speaker ~16
IOC6-1
SPC500A1
IOC(I/O) VDD IOB(I/O) AUD2
Speaker ~16
IOB3-0 IOD7-0
IOB3-0 0.1 IOD7-0
0.1
IOD (I/O) VSS RESET
IOD (I/O)
VSS RESET
R1 VDD 50K
Application Circuit Note (4)
R2 VDD 50K
RESET 0.1 0.1
RESET
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SPC500A1 Application circuit with Serial Interface I/O Application
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C5
C3
15
Rev.: 1.0
1999.11.04
SPC500A1
PAD ASSIGNMENT AND LOCATIONS
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PAD Assignment
Chip Size: 2550 m x 3380 m This IC substrate should be connected to VSS
Note: To ensure that the IC functions properly, bond all VDD, VSS, AVDD and AVSS pins.
Ordering Information Product Number SPC500A1-nnnnV-C Note1: Code number (nnnnV) is assigned for customer. Note2: Code number (nnnn = 0000 - 9999); version (A = A - Z). Package Type Chip form
NOTE: SUNPLUS TECHNOLOGY CO., LTD reserves the right to make changes at any time without notice in order to improve the design and performance and to supply the best possible product.
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SPC500A1
PAD Locations
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Pad No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
Pad Name VSS RESET IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 VSS VDD XO XI AUD1 VDD AUD2 TEST IOD7 IOD6 IOD5 IOD4 IOD3 IOD2 IOD1 IOD0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
X -1116 -1130 -1130 -1130 -1130 -814 -659 -507 -352 -201 -51 144 361 663 1090 1063 1121 1121 1121 1121 1121 1121 1121 1121 1121 1121 1121 1121 1121 1121 1121 1121 1121
Y -1041 -1317 -1473 -1624 -1779 -1774 -1774 -1774 -1774 -1802 -1743 -1802 -1802 -1781 -1791 -1457 -1174 -1023 -864 -713 -555 -403 -245 -93 65 217 375 527 685 836 992 1143 1298
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SPC500A1
DISCLAIMER
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The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by
description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements,
e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. document are for reference purposes only. Please note that application circuits illustrated in this
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Rev.: 1.0
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